Integrated circuits industry and fabrication involve the formation of semiconductor wafers, integrated circuits and chip package. With the advent of Ultra Large Scale Integrated (ULSI) circuits technologies, it has been a trend to scale down the geometry dimension of semiconductor devices and increase the density of semiconductor devices per unit area of silicon wafer. Thus, the sizes of devices, such as memory cells, have gotten smaller and smaller such that the area available for a single device has become very small. For example, the area for forming a dynamic random access memory cell has reduced to sub-micron meter range for achieving higher chip density. Further, the manufacturers of the devices are striving to reduce the sizes while simultaneously increasing their speed.
Developments in interconnect and packing have been quite modest in comparison. The renewed interest in high density hybrid is driven by the requirement to handle large numbers of IC interconnections, the increasing clock rate of digital systems and the desire to pack greater functionality into smaller spaces. Therefore, the number of a package's leads becomes more and more.
Typically, a chip can be connected to a substrate using a method called flip chip assembly. First, in the flip chip assembly, a plurality of metal bumps are formed on bonding pads of the chip. Then, the chip is flipped such that the metal bumps are aligned to the bonding pads of a substrate. Using a thermal pressure process, the metal bumps are connected to the bonding pad of the substrate. However, in many cases, stress is generated between the interface of metal bump and chip, and the interface between the substrate and the metal bump due to the mismatch of the coefficients of thermal expansion (CTE).
One of the ways to solves the problem associated with the CTE mismatch is underfill process. As shown in FIG. 1, in the conventional underfill process, encapsulating material 8 is filled in the space among the chip 4, the substrate 2 and the metal bumps 6. How the encapsulating material 8 is filled under the chip 4 will be described as follows. Turning to FIGS. 2A and 2B, initially, the chip 4 is connected to the substrate 2 using aforementioned method. Then, the encapsulating material 8 is coated at the one or two side(s) of the chip 4 by using supplying means 10. Typically, the encapsulating material 8 is a kind of liquid encapsulating material. Referring to FIG. 2C and 2D, the liquid encapsulating material 8 will flow and fill into the space between the chip 4 and the substrate 2 due to the capillary action. The flowing directions of the liquid encapsulating material 8 are indicated by arrows in FIG. 2C and 2D. Because the density of the metal bumps formed on the chip 4 is not uniform, air may be trapped under the chip 4 during the liquid encapsulating process. Thus, voids will be generated in the liquid encapsulating material 8 that is under the chip. This results the reliability of the semiconductor chip. Further, in order to achieve the purpose of coating the liquid encapsulating material 8 on the substrate 2, the space between chips must be large enough for coating the liquid encapsulating material 8. Thus, it limits the increase of density of semiconductor chips 4 per unit area of the substrate 2. In addition, the flowing path of the liquid encapsulating material 8 is too long for the underfill process. Assume that the dimension of the chip 4 is "a". Then, the longest flowing path of the liquid encapsulating material 8 is about root means square of a.
Turning to FIG. 1, the liquid encapsulating material 8 includes non-organic material 8a that will stay at the bottom of the liquid encapsulating material 8. The other compounds, such as organic polyimide 8b is on the non-organic material 8a. That is because that the density of the non-organic material 8a is highest than other compounds in the liquid encapsulating material 8. In another words, the organic polyimide 8b is adjacent to the chip 4 and the non-organic material 8a is located on the substrate 2. Generally speaking, the substrate2 is composed of Fr4 printed circuit board (PCB). The CTE of the substrate 2 is about 20-30 ppm/centigrade, and the CTE of the non-organic material 8a is about 7 ppm/centigrade. Further, the CTEs of the chip 4 and the organic polyimide 8b are about 2.5 and 50-60 ppm/centigrade, respectively. Therefore, the problem associated with the CTE mismatch is serious in the conventional structure. The chip 4 or the liquid encapsulating material 8 will be delamination from the substrate 2.
What is required is a method to reduce the CTE problem and to increase the reliability of the underfill process for a chip.